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Agilent HDMP-0552 Quad Port Bypass Circuit with CDR and Data Valid Detection
For Fibre Channel Arbitrated Loops
Data Sheet
Features * Supports 1.0625/2.125 GBd Fibre Channel operation * Quad PBC/CDR in one package * CDR location determined by choice of cable input/output * Amplitude valid detection on FM_NODE[0] input * Data valid detection on FM_NODE[0] input - Run length violation detection - Comma detection - Configurable for both singleframe and multi-frame detection * Speed select pin for 1 or 2 GBd operation * Single REFCLK for 1 or 2 GBd operation * CDR selectable via external pin * Enable/disable equalizers on all inputs * Enable/disable selected highspeed output drivers * High speed LVPECL I/O * Buffered line logic (BLL) outputs (no external bias resistors required) * 1.1 W typical power at VCC = 3.3 V * Advanced 0.35 BiCMOS technology * 64 Pin, 10 mm, low cost plastic QFP package Applications * RAID, JBOD, BTS cabinets * 1=> 1-4 serial buffer with or without CDR
Description The HDMP-0552 is a Quad Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. See Figure 1 for block diagram. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. A PBC consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk bypassed." When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the
HDMP-0552's TO_NODE[n] differential output pins to the Disk Drive Transceiver IC (for example, an HDMP-263x) Rx differential input pins. Data from the Disk Drive Transceiver IC Tx differential output pins goes to HDMP-0552's FM_NODE[n] differential input pins. Figure 2 and Figure 3 show connection diagrams for disk drive array applications. When the "disk bypassed" mode is selected, the disk drive is either absent or nonfunctional, and the loop bypasses the hard disk. Multiple HDMP-0552's may be cascaded or connected to other members of the HDMP-04xx family through the FM_LOOP and TO_LOOP pins to create loops for arrays of disk drives greater than 4. See Table 3 to identify which of the 5 cells (0:4) provides FM_LOOP, TO_LOOP pins (cell connected to cable).
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
Combinations of Quad PBCs can be utilized to accommodate any number of hard disks. The unused cells in a quad may be bypassed with pulldown resistors on the BYPASS[n]- pins for these cells. Additional power savings possible by turning off unused output drives. Please refer to BLL output section on page 3. An HDMP-0552 can be wired as a single or double mux cell with a CDR. It may also be used as a single or double mux cell without a CDR. All TO_NODE outputs of the HDMP-0552 are of equal strength. Therefore, this part may be used as a 1=>1- 4 buffer. The design of HDMP-0552 allows for placement of the CDR at any location with respect to hard disk slots. For example, if BYPASS[0]pin is tied to VCC and hard disk slots A to D are connected to PBC cells 1 to 4 in the same order, the CDR function is performed at entry to the HDMP-0552 (Figure 2). To achieve a CDR function at exit from the HDMP-0552, BYPASS[1]- must be tied to VCC and hard disk slots A to D must be connected to PBC cells 2, 3, 4, 0 in that order (Figure 3). Table 3 shows all possible connections. In case of CDR at entry, a Signal Detect (SD) pin shows the status of the signal at the incoming cable. The recommended method of setting the BYPASS[i]- pins HIGH is to drive them with a high-impedance signal. Internal pull-up resistors force the BYPASS[i]- pins to VCC. HDMP-0552 Block Diagram CDR The Clock and Data Recovery (CDR) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. An automatic locking feature allows the CDR to lock onto the input data stream without external training controls. It does this by 2
continually frequency locking onto the reference clock (REFCLK) and then phase locking onto the input data stream. Once bit-locked, the CDR generates a high-speed sampling clock. This clock is used to sample or repeat the incoming data to produce the CDR output. The CDR jitter specifications listed in this data sheet assume an input that has been 8B/10B encoded. Data Valid Output The outgoing data from the CDR is checked for two types of errors. First, the data is checked for "Run Length Violations" (RLV), which are defined as a consecutive bit sequence greater than five. In addition, the data is checked for "No Comma Detected" (NCD), which is defined as no comma within a 215 bit frame. If neither of these errors occur, the data is considered valid Fibre Channel data, and FM_NODE[0]_DV is driven HIGH. For reporting errors, the data valid (DV) block contains a 215bit counter to provide a frame clock. All errors are reported relative to the rising edge of this internally generated clock. There are two LVTTL inputs for configuring the data validity checking. When MODE_DV is HIGH, the data input for the CDR comes from FM_NODE[0]. In this mode, the FM_NODE[0] input is checked for data validity. In addition, the FM_NODE[0]_DV LVTTL output can be used to drive BYPASS[0]- signal. In this configuration, when the data is invalid, the CDR output will be bypassed and the data from TO_NODE[0] will be passed on instead. When MODE_DV is LOW, the data validity checking is still taking place on output of the CDR; however, this data may be from another input besides FM_NODE[0]. In addition, the
CDR output data will always be passed on to TO_NODE[1] in this mode. Lastly, the LVTTL input FSEL selects single versus multi-frame operation of the DV block. For example, when FSEL is LOW, the FM_NODE[0]_DV output will be driven HIGH after 215 bits of good data. Similarly, FM_NODE[0]_DV will be driven LOW after one 215 bit sequence containing errors. This is "single frame" operation. When FSEL is HIGH, the DV block is operating in "multi-frame", or four frame, mode. In this mode, the FM_NODE[0]_DV will be driven HIGH only after four consecutive frames of valid data. Once HIGH, FM_NODE[0]_DV will only be driven LOW after four consecutive 215-bit frames containing errors. REFCLK Input and REF_RATE Control The LVTTL REFCLK input provides a reference oscillator for frequency acquisition of the CDR. The REFCLK frequency should be 53.125 Mhz or 106.25 Mhz +100 ppm. Set REF_RATE = 0 for a 53 Mhz and set REF_RATE = 1 for 106 MHz references. Either reference frequency can be used for both 1 GBd or 2 GBd rates. Amplitude Valid Output The Amplitude Valid (AV) block detects if the incoming data on FM_NODE[0]+ is valid by examining the differential amplitude of that input. The incoming data is considered valid and FM_NODE[0]_AV is driven HIGH, as long as the amplitude is greater than 200 mV (differential peak-to-peak). FM_NODE[0]_AV is driven LOW as long as the amplitude of the input signal is less than 100 mV (differential peak-to-peak). When the amplitude of the input signal is between 100 and 200 mV (differential peak-topeak), FM_NODE[0]_AV is unpredictable.
Equalizer Input All FM_NODE[n]+ high-speed differential inputs have an equalization setting to offset the effects of skin loss and dispersion on PCBs. This function is independently controllable for each input port using the EQ_SEL and NDx (x = 0-4) pins. The default setting for the equalization is TRUE. Equalization maybe set to FAULT for individual inputs by forcing EQ_SEL low and NDx (where x = port number) low for each port that the equalization setting is desired to be false. It is a logic OR function. For instance, forcing EQ_SEL, ND2 & ND3 pins low will turn off the equalization setting at FM_NODE[2]+ and FM_NODE[3]+ while the equalization setting will remain on for ports 0, 1 and 4.
FM_NODE [1] FM_NODE [2] BYPASS [1] BYPASS [2] TO_NODE [1] TO_NODE [2]
The EQ_SEL and NDx (x = 0-4) pins are LVTTL and contain internal pull-up circuitry. To force a pin low each pin should be connected to GND through a 1 kW resistor. Otherwise, these inputs should be left to float. In this case, the internal pull-up circuitry will force them high. BYPASS[n]- Input The active low BYPASS[n]- inputs control the data flow through the HDMP-0552. All BYPASS pins are LVTTL and contain internal pull-up circuitry. To bypass a port, the appropriate BYPASS[n]pin should be connected to GND through a 1 kW resistor. Otherwise, the BYPASS[n]inputs should be left to float. In this case, the internal pull-up circuitry will force them high.
FM_NODE [3] FM_NODE [4] BYPASS [3] BYPASS [4] TO_NODE [3] TO_NODE [4]
BLL Output All TO_NODE[n]+ high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination. Therefore, no external bias resistors are required. The BLL outputs on the HDMP-0552 are of equal strength. Unused outputs should be turned off independently. This reduces power and reduces the potential for crosstalk effects caused by incorrect terminations. If the unused outputs are not turned off they should be differentially terminated. The value of the termination resistor should match the PCB trace differential impedance. Each output port is set to active or inactive by the OUT_SEL and NDx (x = 0-4) pins.
FM_NODE [0]
EQU 1 0
EQU
EQU
EQU
EQU
TTL
TTL
TTL
BLL
BLL
BLL
BLL
TTL
1 0
1 0
1 0
1 0
0 0 1 1
CDR DV
CPLL
BLL
TO_NODE [0]
AV
TTL
SSTL
TTL
TTL
TTL
TTL
TTL
FM_NODE [0]_DV
BYPASS [0] -
CDR_RATE
MODE_DV
REF_RATE
CDR_SEL
REFCLK
FSEL
TTL
Figure 1 - Block Diagram of HDMP-0552
3
FM_NODE [0]_AV
TTL
Output port active is the default condition. Each output port may be set to inactive by forcing OUT_SEL low and NDx (where x = port number) low. It is a logic OR function. For instance, forcing OUT_SEL, ND1 & ND4 pins low
will turn off output ports TO_NODE[1]+ and TO_NODE[4]+ while output ports 0,2 and 3 will remain on. When an output port is off both output terminals will pull high to approximately VCC.
The OUT_SEL and NDx (x = 0-4) pins are LVTTL and contain internal pull-up circuitry. To force a pin low each pin should be connected to GND through a 1 kW resistor. Otherwise, these inputs should be left to float. In this case, the internal pull-up circuitry will force them high.
Hard Disk A
Hard Disk B
Hard Disk C
Hard Disk D
FM_NODE [0] = FM_LOOP TO_NODE [0] = TO_LOOP
FM_NODE [1]
FM_NODE [2]
FM_NODE [3]
BYPASS [1]-
BYPASS [2]-
BYPASS [3]-
FM_NODE [4]
TO_NODE [1]
TO_NODE [3]
TO_NODE [2]
TO_NODE [4]
1
1 0
2
1 0
3
1 0
4
BYPASS [4]-
1 0
0
CDR
Figure 2 - Connection Diagram for CDR at First Cell
Hard Disk A
Hard Disk B
Hard Disk C
Hard Disk D
FM_NODE [1] = FM_LOOP
TO_NODE [1] = TO_LOOP
SERDES
BYPASS [1]- = 1 FM_NODE [2] TO_NODE [2] TO_NODE [3]
SERDES
FM_NODE [3] TO_NODE [4]
SERDES
FM_NODE [4] TO_NODE [0]
SERDES
FM_NODE [0]
BYPASS [2]-
BYPASS [3]-
1
1 0
2
1 0
3
1 0
4
BYPASS [4]-
1 0
0
CDR
Figure 3 - Connection Diagram for CDR at Last Cell
4
BYPASS [0]1 0
BYPASS [0]- = 1
1 0
SERDES
SERDES
SERDES
SERDES
Table 1 - Pin Definitions for HDMP-0552. Refer to Figure 4 for pin layout
Pin Name MODE_DV Pin 24 Pin Type I-LVTTL Pin Description Data Valid Detect Mode: To allow data valid detection, float MODE_DV HIGH. To configure chip for "CDR anywhere" capability, connect MODE_DV to GND through a 1 kW resistor. Frame Select: To configure single-frame operation of the data valid and amplitude valid detection circuits, connect FSEL to GND through a 1 kW resistor. To configure multi-frame (4-frame) operation of the data valid and amplitude valid detection circuits, float FSEL HIGH. Data Valid: Indicates valid Fibre Channel Data on the FM_NODE[0] inputs when HIGH. Indicates either run length violation error or no comma detected when LOW. Amplitude Valid: Indicates acceptable signal amplitude on the FM_NODE[0] inputs. Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable input.
FSEL
25
I-LVTTL
FM_NODE[0]_DV
23
O-LVTTL
FM_NODE[0]_AV TO_NODE[0]+ TO_NODE[0]TO_NODE[1]+ TO_NODE[1]TO_NODE[2]+ TO_NODE[2]TO_NODE[3]+ TO_NODE[3]TO_NODE[4]+ TO_NODE[4]FM_NODE[0]+ FM_NODE[0]FM_NODE[1]+ FM_NODE[1]FM_NODE[2]+ FM_NODE[2]FM_NODE[3]+ FM_NODE[3]FM_NODE[4]+ FM_NODE[4]BYPASS[0]BYPASS[1]BYPASS[2]BYPASS[3]BYPASS[4]CDR_SEL
59 57 56 32 31 35 34 44 43 47 46 54 53 29 28 38 37 41 40 51 50 55 30 36 42 49 10
O-LVTTL HS_OUT
HS_IN
Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable output.
I-LVTTL
Bypass Inputs: For "disk bypassed" mode, connect BYPASS[n]- to GND through a 1 kW resistor. For "disk in loop" mode, float HIGH.
I-LVTTL
CDR_RATE
11
I-SSTL2
REF_RATE
12
I-LVTTL
REFCLK CPLL1 CPLL0 EQ_SEL
14 16 17 61
I-LVTTL C C I-LVTTL
CDR Select: To configure the chip with the CDR bypassed, connect CDR_SEL to GND through a 1 kW resistor. To configure the chip with the CDR in the loop, float CDR_SEL HIGH. CDR Rate: To configure the chip for 1 GBd operation, connect CDR_RATE to GND through a 1 kW resistor. To configure the chip for 2 GBd operation, float CDR_RATE HIGH. Reference Rate: Float REF_RATE HIGH for a reference rate of 106.25 MHz and connect REF_RATE to GND via a 1 kW resistor for a reference rate of 53.125 MHz. Reference Clock: A user-supplied clock reference used for frequency acquisition in the Clock and Data Recovery (CDR) circuit. Loop Filter Capacitor: A loop filter capacitor for the internal Clock and Data Recovery (CDR) circuit must be connected across the CPLL1 and CPLL0 pins. Recommended value is 0.1 F. Equalizer Select: Allows user to select/deselect equalization on any input.
5
Table 1 (continued) - Pin Definitions for HDMP-0552. Refer to Figure 4 for pin layout
Pin Name OUT_SEL ND0
Pin 60 64
Pin Type I-LVTTL I-LVTTL
ND1
63
I-LVTTL
ND2
62
I-LVTTL
ND3
20
I-LVTTL
ND4
21
I-LVTTL
TDO TDI nTRST TMS TCK NC GND
VCC
VCCA VCCHS
2 3 4 5 6 19 07 09 15 18 26 39 52 01 13 22 27 48 08 33 45 58
O-LVTTL I-LVTTL I-LVTTL I-LVTTL I-LVTTL NC S
Pin Description Output Select: Allows user to turn on/off any output driver. Node 0 Input: In combination with EQ_SEL, allows the user to select/deselect equalization on FM_NODE[0] inputs. In combination with OUT_SEL, allows the user to turn on/off the TO_NODE[0] output driver. Float HIGH to select Node 0, or connect to GND through a 1 kW resistor to deselect Node 0. Node 1 Input: In combination with EQ_SEL, allows the user to select/deselect equalization on FM_NODE[1] inputs. In combination with OUT_SEL, allows the user to turn off/on the TO_NODE[1] output driver. Float HIGH to select Node 1, or connect to GND through a 1 kW resistor to deselect Node 1. Node 2 Input: In combination with EQ_SEL, allows the user to select/deselect equalization on FM_NODE[2] inputs. In combination with OUT_SEL, allows the user to turn off/on the TO_NODE[2] output driver. Float HIGH to select Node 2, or connect to GND through a 1 kW resistor to deselect Node 2. Node 3 Input: In combination with EQ_SEL, allows the user to select/deselect equalization on FM_NODE[3] inputs. In combination with OUT_SEL, allows the user to turn off/on the TO_NODE[3] output driver. Float HIGH to select Node 3, or connect to GND through a 1 kW resistor to deselect Node 3. Node 4 Input: In combination with EQ_SEL, allows the user to select/deselect equalization on FM_NODE[4] inputs. In combination with OUT_SEL, allows the user to turn off/on the TO_NODE[4] output driver. Float HIGH to select Node 4, or connect to GND through a 1 kW resistor to deselect Node 4. JTAG JTAG JTAG JTAG JTAG No Connect. Ground: Normally 0 V.
S
Digital Power Supply pin.
S S S S
Analog Power Supply pin. Cells 1 and 2 High Speed Output Pins Power Supply. Cells 3 and 4 High Speed Output Pins Power Supply. Cell 0 High Speed Output Pins Power Supply.
6
FM_NODE [0]_AV
FM_NODE [0] +
FM_NODE [4] +
TO_NODE [0] +
FM_NODE [0] -
FM_NODE [4] -
TO_NODE [0] -
BYPASS [0] -
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCC TD0 TD1 nTRST TMS TCK GND VCCA GND CDR_SEL CDR_RATE REF_RATE VCC REFCLK GND CPLL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 VCC TO_NODE [4] + TO_NODE [4] VCCHS TO_NODE [3] + TO_NODE [3] BYPASS [3] FM_NODE [3] + FM_NODE [3] GND FM_NODE [2] + FM_NODE [2] BYPASS [2] TO_NODE [2] + TO_NODE [2] VCCHS
Agilent HDMP-0552 xxxxxxx-nn S YYWW Rz.zz
BYPASS [4] 44 43 42 41 40 39 38 37 36 35 34 33
OUT_SEL
EQ_SEL
VCCHS
GND
ND0
ND1
ND2
Figure 4 - HDMP-0552 package layout and marking, top view xxxxxxx-nn = wafer lot - build number; S = Supplier Code; YYWW = Date Code (YY = year, WW = work week); Rz.zz = Die Revision; COUNTRY (on back side) = country of manufacture.
CPLL0
GND
NC
ND3
ND4
VCC
FM_NODE [0]_DV
MODE_DV
FSEL
GND
VCC
FM_NODE [1] -
FM_NODE [1] +
BYPASS [1] -
TO_NODE [1] -
TO_NODE [1] +
7
Table 2 - I/O Type Definitions
I/O Type I-LVTTL O-LVTTL HS_OUT HS_IN C S NC I-SSTL2
Definition LVTTL Input LVTTL Output High Speed Output, BLL High Speed Input External circuit node Power supply or ground No connect SSTL2 compatible, non-terminated
Please refer to Figures 5 and 6 for simplified I/O diagrams.
Table 3 - Pin Connection Diagram to Achieve Desired CDR Location
Hard Disks Connection to PBC cells CDR position (x) Cell connected to Cable
ABC 1 23 xA B C 0
D 4 D
ABC 012 Ax B C 4
D 3 D
A 4 A 3
BCD 012 Bx C D
A 3 A 2
B 4 B
CD 01 Cx D
A 2 A 1
B 3 B
C 4 C
D 0 Dx
x denotes CDR position with respect to hard disks. For example A x B C D means the CDR is between disk A and disk B.
HDMP-0552 Electrical Specifications Absolute Maximum Ratings Ta = +25C , except as specified. Operation in excess of any of these conditions may result in permanent damage to this device.
Symbol VCC VIN, LVTTL VIN,HS_IN IO,LVTTL Tstg Tj
Parameter Supply Voltage LVTTL Input Voltage HS_IN Input Voltage LVTTL Output Current Storage Temperature Junction Temperature
Units V V V mA C C
Minimum -0.7 -0.7 2.0 -65 0
Maximum 4.0 5.0 VCC +13 +150 +125
VDD
VDD
GND OUTPUT O INPUT I
GND
GND
Figure 5 - Simplified Digital I/O Circuit Diagrams
8
Guaranteed Operating Rates Ta = 0C to Tc = +80C , VCC = 3.15 V to 3.45 V
Serial Clock Rate FC (MBd) Minimum Maximum 1,040 1,080 2,080 2,160
HS_OUT 75 W VCCHS VCC +TO_NODE Zo = 75 W 0.01 F VCC VCC +FM_NODE
HS_IN
+ + -
-TO_NODE
ESD PROTECTION
-FM_NODE Zo = 75 W 0.01 F GND
ESD PROTECTION
2xZo = 150 W
GND
GND
GND
NOTE: HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT.
Figure 6 - O-BLL and I-BLL Simplified Circuit Schematic
Clock and Data Recovery Circuit (CDR) Reference Clock Requirements Ta = 0C to Tc = +80C , VCC = 3.15 V to 3.45 V
Symbol f f Ftol Symm
Parameter Nominal Frequency (REF_RATE = 1) Nominal Frequency (REF_RATE = 0) Frequency Tolerance Symmetry (duty cycle)
Units Minimum Typical MHz 106.25 MHz 53.125 ppm -100 % 40
Maximum
+100 60
DC Electrical Specifications Ta = 0C to Tc = +80C , VCC = 3.15 V to 3.45 V
Symbol VIH1,LVTTL VIL,LVTTL VOH1,LVTTL VOL,LVTTL IIH,LVTTL IIL,LVTTL ICC
Parameter LVTTL Input High Voltage Range LVTTL Input Low Voltage Range LVTTL Output High Voltage Range, IOH = -400 uA LVTTL Output Low Voltage Level, IOL = 1 mA Input High Current (Magnitude), VIN = 2.4 V, VCC = 3.45 V Input Low Current (Magnitude), VIN = 0.4 V, VCC = 3.45 V Total Supply Current, Ta = +25C
Units V V V V uA uA mA
Minimum Typical 2.0 0 2.2 0 0 5 0 65 320
Maximum Vcc 0.8 Vcc 0.6 40 300
Note: 1. LVTTL I/Os 5 V tolerant.
9
AC Electrical Specifications Ta = 0C to Tc = +80C , VCC = 3.15 V to 3.45 V
Symbol tdelay1 tdelay2 tr,LVTTLin tf,LVTTLin tr, LVTTLout tf, LVTTLout trs2,HS_OUT tfs2,HS_OUT trd2,HS_OUT tfd2,HS_OUT VIP,HS_IN VOP,HS_OUT
Parameter Total Loop Latency from FM_NODE[0] to TO_NODE[0] Per Cell Latency from FM_NODE[x] to TO_NODE[x+1] Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V Output LVTTL Rise Time Range, 0.8 V to 2.0 V, 10 pF Load Output LVTTL Fall Time Range, 2.0 V to 0.8 V, 10 pF Load HS_OUT Single-Ended Rise Time HS_OUT Single-Ended Fall Time HS_OUT Differential Rise Time HS_OUT Differential Fall Time HS_IN Input Peak to Peak Required Differential Voltage Range HS_OUT Output Pk-Pk Diff. Voltage Range (Zo = 75 W)
Units ns ns ns ns ns ns ps ps ps ps mV mV
Minimum Typical 1.5 0.4 2 2 1.5 2.0 44 65 44 65 44 65 44 65 200 1100 1400
Maximum 4.0 0.8
110 110 110 110 2000 2000
Note: 2. Measured from 20% to 80% levels with trace length 3", Fr-4 board, Zo= 50 ohms and a 50 ohm and 200 fF termination. Please refer to Figure 6 for simplified circuit schematic.
Power Dissipation and Thermal Resistance Ta = 0C to Tc = +80C , VCC = 3.15 V to 3.45 V
Symbol PD qjc
Parameter Power Dissipation Thermal Resistance, Junction to Case
Units W C/W
Typical 1.1 2.5
Maximum 1.28
Output Jitter Characteristics Ta = 0C to Tc = +80C , VCC = 3.15 V to 3.45 V
Symbol RJ DJ
Parameter Random Jitter at TO_NODE pins (1 sigma rms) Deterministic Jitter at TO_NODE pins (pk-pk)
Units ps ps
Typical 3.5 10
Please refer to Figures 8 and 9 for jitter measurement setup information.
Figure 7 - Eye Diagram obtained differentially at 2.125 GBd FROM NODE(0) TO NODE(2) with 50 W termination
10
Locking Characteristics Ta = 0C to Tc = +80C , VCC = 3.15 V to 3.45 V
Parameter Bit Sync Time (phase lock) Frequency Lock at Powerup
Units bits s
Maximum 2500 500
RANDOM JITTER 70841B DATA PATTERN GENERATOR
K28.7 0011111000
2 BIAS
HDMP-0552 FM_NODE[0] BYPASS - [0] BYPASS - [1] BYPASS - [2] BYPASS - [3] BYPASS - [4] TO_NODE[1] VCC
CLOCK
REF CLK
2.125 GHz 70311A CLOCK SOURCE
1.4 VARIABLE DELAY
1/20
2 CH 1/2 TRIGGER 83480A DIGITAL COMMUNICATION ANALYZER
106.25 MHz
Figure 8 - Setup for Measurement of Random Jitter
DETERMINISTIC JITTER 70841B DATA PATTERN GENERATOR
+K28.5 -K28.5
2 BIAS
HDMP-0552 FM_NODE[0] BYPASS - [0] BYPASS - [1] BYPASS - [2] BYPASS - [3] BYPASS - [4] TO_NODE[1] VCC
CLOCK
REF CLK
2.125 GHz 70311A CLOCK SOURCE
1.4 VARIABLE DELAY
1/20
2 CH 1/2 1/2 TRIGGER 83480A DIGITAL COMMUNICATION ANALYZER
106.25 MHz
Figure 9 - Setup for Measurement of Deterministic Jitter
11
Package Information
Item Package Material Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (Seating Plane Method) Details Plastic 85% Tin, 15% Lead 300-800 micro-inches 0.08 mm maximum 0.08 mm maximum
Mechanical Dimensions
D1
PIN No. 1 ID
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42
E1
TOP VIEW
41 40 39 38 37 36 35 34 33
E
D
c
A2 A1
A
SEATING PLANE
b e L
0.25 GAUGE PLANE
Dimensional Parameter A (millimeters) Value 2.45 Tolerance MAX
A1 0.25 MIN
A2 2.00 +0.10, -0.05
D/E 13.20 0.25
D1/E1 10.00 0.10
L 0.88 +0.15, -0.10
b 0.22 0.05
c 0.17 MAX
e 0.50 BASIC
Figure 10 - HDMP-0552 Package Drawing
www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. October 15, 2001 5988-3998EN

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